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PACDN009 5 Channel ESD Protection Array
Features
* * * * * * * Five channels of ESD protection 8 kV contact, 15 kV air ESD protection per channel (IEC 61000-4-2 standard) 15 kV of ESD protection per channel (HBM) Low loading capacitance (3pF typical) Low leakage current is ideal for battery-powered devices Available in miniature 8-lead MSOP package Lead-free version available
Product Description
The PACDN009 is a diode array designed to provide 5 channels of ESD protection for electronic components or sub-systems. Each channel consists of a pair of diodes which steers an ESD current pulse to either the positive (VP) or negative (VN) supply. The PACDN009 protects against ESD pulses up to 15kV Human Body Model (100 pF capacitor discharging through a 1.5K resistor), and 8kV contact discharge, per International Standard IEC 61000-4-2. This device is particularly well-suited for portable electronics (e.g., cellular phones, PDAs, notebook computers) because of its small package footprint, high ESD protection level, and low loading capacitance. It is also suitable for protecting video output lines and I/O ports in computers and peripherals and is ideal for a wide range of consumer electronics products. The PACDN009 is supplied in an 8-lead MSOP package and is available with optional lead-free finishing.
Applications
* * * * * * * Consumer electronic products Cellular phones PDAs Notebook computers Desktop PCs Digital cameras and camcorders VGA (video) port protection for desktop and portable PCs
Typical Application Circuit
Electrical Schematic
3
PACDN009
14568
7
0.22F*
8
VP
7
6
5
I/O Port Buffers
Expansion Connector
VN
N.C.
1
Handheld/PDA ESD Protection
* Capacitor should be placed as close as possible to Pin7
2
3
4
(c) 2004 California Micro Devices Corp. All rights reserved. 09/21/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
1
PACDN009
PACKAGE / PINOUT DIAGRAMS TOP VIEW
CH 1 N.C. VN CH 2
1 2 3 4 8 7 6 5
CH 5 VP CH 4 CH 3
PACDN009 8-lead MSOP Package
Note: This drawing is not to scale.
PIN DESCRIPTIONS
PIN 1 2 3 4 5 6 7 8 NAME CH 1 N.C. VN CH 2 CH 3 CH 4 VP CH 5 TYPE I/O GND I/O I/O I/O Supply I/O DESCRIPTION ESD Channel No connect Negative voltage supply rail or ground reference rail ESD Channel ESD Channel ESD Channel Positive voltage supply rail ESD Channel
Ordering Information
PART NUMBERING INFORMATION
Standard Finish Leads 8 Package MSOP Ordering Part Number1 PACDN009M Part Marking D009 Lead-free Finish Ordering Part Number1 PACDN009MR Part Marking 009R
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
(c) 2004 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
09/21/04
PACDN009
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (VP - VN) Diode Forward DC Current (Note 1) Operating Temperature Range Storage Temperature Range DC Voltage at any channel input Package Power Rating MSOP Package
Note 1: Only one diode conducting at a time.
RATING 6.0 20 -40 to +85 -65 to +150 (VN - 0.5) to (VP + 0.5) 200
UNITS V mA C C V mW
STANDARD OPERATING CONDITIONS
PARAMETER Operating Temperature Range Operating Supply Voltage (VP - VN) RATING -40 to +85 0 to 5.5 UNITS C V
ELECTRICAL OPERATING CHARACTERISTICS(SEE NOTE 1)
SYMBOL IP VF VESD PARAMETER Supply Current Diode Forward Voltage ESD Protection Peak Discharge Voltage at any channel input, in system a) Human Body Model, MIL-STD-883, Method 3015 b) Contact Discharge per IEC 61000-4-2 c) Air Discharge per IEC 61000-4-2 Channel Clamp Voltage Positive Transients Negative Transients Channel Leakage Current Channel Input Capacitance @ 1 MHz, VP=5V, VN=0V, VIN=2.5V; Note 2 applies CONDITIONS (VP-VN)=5.5V IF = 20mA Note 3 Notes 2,4 Note 5 Note 5 @15kV ESD HBM VP + 13.0 VN - 13.0 V V A pF 0.65 MIN TYP MAX 10 0.95 UNITS A V
15 8 15
kV kV kV
VCL
ILEAK CIN
0.1
3
1.0
5
Note 1: All parameters specified at TA=25C unless otherwise noted. VP = 5V, VN = 0V unless noted. Note 2: These parameters guaranteed by design and characterization. Note 3: From I/O pins to VP or VN only. VP bypassed to VN with a 0.22F ceramic capacitor (see Application Information for more details). Note 4: Human Body Model per MIL-STD-883, Method 3015, CDischarge = 100pF, RDischarge = 1.5K, VP = 5.0V, VN grounded. Note 5: Standard IEC 61000-4-2 with CDischarge = 150pF, RDischarge = 330, VP = 5.0V, VN grounded.
(c) 2004 California Micro Devices Corp. All rights reserved. 09/21/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
3
PACDN009
Performance Information
Input Capacitance vs. Input Voltage
5 4
CIN (pF)
3 2 1 0 0 1 2 3 4 5
VIN
(VP = 5V, VN = 0V, 0.1 F chip capacitor between VP and VN)
Typical Variation of CIN vs. VIN
(c) 2004 California Micro Devices Corp. All rights reserved.
4
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
09/21/04
PACDN009
Application Information
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances on the Supply/ Ground rails as well as the signal trace segment between the signal input (typically a connector) and the ESD protection device. Refer to Figure 1, which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductances back to the power supply are represented by L1 and L2. The voltage VCL on the line being protected is:
VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt + L2 x d(IESD ) / dt
with ROUT equal to 1 ohm, we would see a 10V increment in VCL for a peak IESD of 10A. If the inductances and resistance described above are close to zero, the rail-clamp ESD protection diodes will do a good job of protection. However, since this is not possible in practical situations, a bypass capacitor must be used to absorb the very high frequency ESD energy. So for any brand of rail-clamp ESD protection diodes, a bypass capacitor should be connected between the VP pin of the diodes and the ground plane (VN pin of the diodes) as shown in the Application Circuit diagram below. A value of 0.22F is adequate for IEC-61000-4-2 level 4 contact discharge protection (8kV). Ceramic chip capacitors mounted with short printed circuit board traces are good choices for this application. Electrolytic capacitors should be avoided as they have poor high frequency characteristics. For extra protection, connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series inductance inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher than the maximum supply voltage. As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ESD device to minimize stray series inductance.
where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1ns. Here d(IESD)/dt can be approximated by IESD/t, or 30/(1x10-9). So just 10nH of series inductance (L1 and L2 combined) will lead to a 300V increment in VCL! Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically increased negative voltage on the line being protected. Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies exhibit a much higher output impedance to fast transient current spikes. In the VCL equation above, the VSUPPLY term, in reality, is given by (VDC + IESD x ROUT), where VDC and ROUT are the nominal supply DC output voltage and effective output impedance of the power supply respectively. For example,
L2
VP
Additional Information
See also California Micro Devices Application Notes AP209, "Design Considerations for ESD Protection" and AP219, "ESD Protection for USB 2.0 Systems""
POSITIVE SUPPLY RAIL
PATH OF ESD CURRENT PULSE IESD
D1
L1
ONE CHANNEL OF PAC DN009 CHANNEL INPUT
20A
LINE BEING PROTECTED
D2
SYSTEM OR CIRCUITRY BEING PROTECTED
VCL
GROUND RAIL
0A
VN
CHASSIS GROUND
Figure 1. Application of Positive ESD Pulse between Input Channel and Ground
(c) 2004 California Micro Devices Corp. All rights reserved. 09/21/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
5
PACDN009
Application Information (cont'd)
Implementation Examples
ESD events are very high-speed pulses with rise times in the range of 1ns or less. To effectively use the PACDN009, the following design guidelines must be observed (as discussed in the application section): 1) The inductance from the VN and VP connections of the PACDN009 to ground must be very low. This includes the path through the VP decoupling capacitor to ground and the path to the power supply (as discussed above). 2) The inductance between the connector pin to be protected and the PACDN009 channel input pin must be kept to a minimum. If there is a large inductance here, the ESD event will find a lower impedance path which will more likely be through the device to be protected. Figure 2 shows the implementation schematic and Figure 3 shows a possible layout for the PACDN009. In figure 3, notice the large VCC and ground areas with multiple via connections to the underlying reference planes and the positioning of the bypass capacitor. Note how the signal lines to be protected flow from the connector to the PACDN009 and then out to the device to be protected (Figure 3). This daisy chaining provides a low impedance path from the connector to the PACDN009 and a higher impedance path from the PACDN009 to the protected device.
POSITIVE SUPPLY RAIL
D1
CHANNEL INPUT
DECOUPLING CAPCITOR 0.22F LINE BEING PROTECTED
D2
ONE CHANNEL OF PAC DN009
OPTIONAL ZENER DIODE FOR EXTRA PROTECTION
SYSTEM OR CIRCUITRY BEING PROTECTED
POWER SUPPLY
GROUND RAIL
Figure 2. Typical ESD protection implementation
(c) 2004 California Micro Devices Corp. All rights reserved.
6
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
09/21/04
PACDN009
Application Information (cont'd)
Figure 3. PCB Layout Recomendation
(c) 2004 California Micro Devices Corp. All rights reserved. 09/21/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
7
PACDN009
Mechanical Details
Mechanical Package Diagrams MSOP Mechanical Specifications The PACDN009 is supplied in an 8-lead MSOP package. Dimensions are presented below.
8 7 TOP VIEW
D
6 5
For complete information on the MSOP-8 package, see the specific California Micro Devices Package Information document. H E
Pin 1 Marking
PACKAGE DIMENSIONS
Package Leads Dimensions A A1 B C D E e H L # per tube # per tape and reel 2.90 2.90 4.78 0.52 Millimeters Min 0.87 0.05 0.18 3.10 3.10 4.98 0.54 0.114 0.114 0.188 0.017 Max 1.17 0.25 Min 0.034 0.002 MSOP 8 Inches Max 0.046 0.010
SEATING PLANE 1 2
3
4
SIDE VIEW
A A1 B e
END VIEW
0.30 (typ)
0.012 (typ) 0.007 0.122 0.122 0.196 0.025
0.65 BSC
0.025 BSC
C
80 pieces* 4000 pieces Controlling dimension: inches
L Package Dimensions for MSOP-8
* This is an approximate number which may vary.
(c) 2004 California Micro Devices Corp. All rights reserved.
8
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
09/21/04

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